On May 23rd, it is expected that NVIDIA will release the next generation of the RTX 50 series in the fourth quarter of this year. Some say that only the flagship RTX 5090 will be released, while others suggest that the RTX 5080 will come first followed by the RTX 5090. There is a high probability that even NVIDIA has not fully decided yet.
Previously, there were leaks indicating that the RTX 50 series would upgrade to GDDR7 memory. According to the latest information, the RTX 5090 FE Founders Edition not only features GDDR7 memory but also has a more densely packed configuration. Positioned above the GB202 GPU core are 4 chips, with 5 on each side, and 2 below, totaling up to 16 chips.
In comparison to the RTX 4090 Founders Edition with 3 chips above, 4 on each side, and 2 below, an additional chip has been added in each direction.
With each chip having a capacity of 2GB, the total memory of the RTX 5090 reaches 32GB, an increase of up to one-third.
RTX 4090 FE
RTX 5090 FE Memory Layout Schematic
In order to accommodate such a large amount of memory, as well as potentially higher power consumption, the PCB design of the RTX 5090 FE reference card is no longer the current single-piece design, but instead consists of up to three separate pieces!
This approach is taken to allow for more space and to enable double-sided cooling, whereas the current RTX 40/30 series all feature single-sided cooling.
As a result, the number of fans is likely to increase to three, and the thickness may approach or even reach four slots.
However, the specific design of the three PCBs is still unclear at the moment. It has only been mentioned that the memory cannot be accommodated when the PCB lies flat, so it is likely that it will be rotated 90 degrees parallel to the motherboard, with a separate sub-card used for the interface section, similar to the unreleased RTX 4090 Ti or RTX Ada.
And that's not all – an interesting detail is the mention of an increase in memory bus width, indicating a potential shift from 384-bit to 512-bit, as previously speculated.
We know that increasing the memory bus width not only requires adding more transistors inside the chip but also necessitates additional components on the PCB, which is a key reason for transitioning to a three-PCB setup.
