The conundrum of combinatorial optimization problems permeates through various facets of social and industrial realms, including autonomous driving, smart logistics, and communication networking. These conundrums typically exhibit the hallmark of nondeterministic polynomial-time complexity, posing immense challenges to classical computation. While quantum annealing computers have made breakthroughs in specific domains, their large-scale applications are severely constrained by the necessity for extremely low-temperature operating environments and the immature state of superconducting technology.
In scenarios where achieving complete quantum realization remains elusive, amalgamating quantum with classical approaches emerges as an immensely promising technological pathway. Recently, Associate Professor Zhuojun Chen and his team from the School of Semiconductor at Hunan University have successfully developed an ultra-low-power, all-digital annealing processor chip. This chip employs an innovative computing architecture that integrates storage and computation, thereby realizing quantum-inspired heuristic annealing algorithms.
A quantum-inspired simulated annealing processor chip is at work. (Image provided by interviewee)
The study maps real-world combinatorial optimization problems onto the King's Graph spin network topology, deploying spin coupling coefficients into the annealing processor chip. After several annealing cycles, the optimal solution to the combinatorial optimization problem can be obtained. The research team innovatively proposes sparse perception spin operations, coupling coefficient reuse technology, and probability flipping function approximation circuits, significantly improving system efficiency and area efficiency.
This processor is fabricated using the SMIC 55nm CMOS process and features 900 spin nodes, supporting a 4-bit spin coupling coefficient width. The energy required for each spin update is only 2.4 femtojoules, and the area for each spin is only 402 square micrometers. Test results indicate that when solving combinatorial optimization problems such as maximum cut sets and image segmentation, the processor is 3 to 4 orders of magnitude faster than state-of-the-art CPUs and consumes 2 to 3 orders of magnitude less power.
Under the microscope: Annealed processor chip. Image provided by the interviewee.
Recent research findings have been published in the IEEE Journal of Solid-State Circuits. The first author of the paper is doctoral student Zhou Yifeng from the School of Physics and Microelectronics at Hunan University, with corresponding authors Chen Zhuojun and Professor Liao Lei from the School of Semiconductor at Hunan University. Hunan University is the sole institution involved.
Reviewers of the paper believe that the circuit design method proposed in the study provides important technical support for quantum-inspired classical computing. The functionality displayed by the annealed processor chip is comprehensive, opening up new avenues for efficiently solving combinatorial optimization problems.
For more information on the paper, visit: IEEE Xplore
