NVIDIA's recent B100/B200 AI GPUs have made a shift from the 4N to the 4NP fabrication process, boosting transistor count from 80 billion to 104/208 billion. This same Blackwell architecture will be carried over to the RTX 50 series gaming GPUs, promising similar advancements.

Latest rumors indicate that the Ampere architecture-based GA102 core, found in the RTX 30 series, will be fabricated on TSMC's 5nm N4 node, not the 3nm N3 node.

However, both the 4N and 4NP nodes are not true 4nm processes, but rather customized versions of the 5nm node. They do offer some improvements over the standard 5nm node, including a 30% increase in transistor density, which justifies the "4N" designation, but it can be confusing.

Furthermore, the L1 cache of GB202 will also be greatly increased, and the specific capacity details are unknown. However, it will definitely exceed the mere 128KB of GA102 and AD102, which means that the throughput of a single SM array will be significantly improved.

GB202 may continue to use a 384-bit memory bus, or it may be upgraded to 512-bit. With the new generation of GDDR7 memory, the bandwidth will expand rapidly. The number of SM arrays is expected to increase significantly from 144 to 192.

In addition, the RTX 50 series will also bring PCIe 5.0 and DisplayPort 2.1.