JEDEC Updates DDR5 Memory Standard: Expands from 6800 to 8800 Mbps, Introduces PRAC Scheme

As of April 19, the JEDEC Solid State Technology Association has released the latest JESD79-5C DDR5 SDRAM standard. This update aims to enhance reliability, security, and performance, catering to a range of applications from high-performance servers to emerging technologies like AI and machine learning. According to pulsestacks, the key features brought by JESD79-5C DDR5 include:

• Expansion of standard timing parameters from 6800 Mbps to 8800 Mbps.
• Extension of DRAM core timing and Tx/Rx AC timing to 8800 Mbps, compared to previous versions which supported a maximum of 6400 timing parameters and up to 7200 DRAM core timing segments.
• Introduction of Self-Refresh Exit Clock Sync to optimize I/O training.
• Inclusion of Dual Die Package (DDP) timing.
• Partial Array Self-Refresh (PASR) is deprecated to address security concerns.

Christopher Cox, chairman of the JEDEC JC-42 committee, stated, "PRAC is a comprehensive solution that helps ensure DRAM data integrity and is part of the DDR5 update. We are working to incorporate this feature into other DRAM product lines within JEDEC."

PRAC, or Per-Row Activation Counting, is designed to improve DRAM data integrity by precisely counting DRAM activations on a per-wordline granularity. When DRAM supporting PRAC detects excessive activations, it alerts the system to pause traffic and take mitigating actions for a specified duration.