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GDDR7's Capacity Stagnates at Just 2GB! A Future First with 3GB

Shang Fang Wen Q Wed, Mar 13 2024 10:26 PM EST

News on March 8th reports that the JEDEC organization has officially announced the technical specifications for GDDR7 memory technology, showing significant improvements in various metrics. However, unexpectedly, the capacity density has not advanced, maxing out at just 2GB, leaving room only for future advancements.

GDDR7 has been upgraded to a four-channel transmission architecture, with per-pin bandwidth increasing to 32-48Gbps. This is a full 2-3 times the rate of GDDR6/6X, achieving a maximum bandwidth of up to 1.5TB/s under a 256-bit width. It also supports on-die ECC, while the voltage has been reduced from 1.35V to 1.2V, further saving on power consumption.

Moreover, signal modulation has been lowered from PAM-4 to PAM-3 to reduce load, and the packaging has been changed to 266 FBGA. s_527aace0c39145c1ab879a48b4ed3fa5.jpg The initial batch of GDDR7 graphics memory will feature a single module capacity of only 2GB (16Gb), identical to the current GDDR6/6X specifications. Therefore, the debut models equipped with NVIDIA RTX 50 series and AMD RX 8000 series will still require a significant amount of memory to achieve large capacities.

Fortunately, JEDEC has outlined plans for higher capacity densities, with upcoming releases expected to include 3GB, 4GB, 6GB, and even 8GB modules. It's noteworthy that the unconventional capacity of 3GB is making its first appearance in this context. s_78339f49d41b40a39fadd93fc5a0d927.jpg The mass production timeline depends on the progress of industry giants such as Samsung, Micron, SK Hynix, and the adoption willingness of NVIDIA and AMD.

It's worth noting that during the GDDR6 era, there were designs for individual chip capacities of 1.5GB, but they were never brought into production. s_0dd0fe2190324f95bb9235b7a8e899b5.jpg

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GDDR5/6/7 Channel Architecture Diagram

Here is the channel architecture diagram for GDDR5, GDDR6, and GDDR7:

GDDR Channel Architecture

This diagram illustrates the communication pathways and connectivity within the GDDR5, GDDR6, and GDDR7 memory modules, providing a visual representation of their channel structures. If you have any specific questions or need further clarification, feel free to ask. s_ba1ce5637d7c43a482fb933ec7f40ab6.png Illustration of the On-Chip ECC Process for GDDR7 s_8fce124decfd48b3ab5733d439974860.png GDDR7 Pinout Diagram