In a surprising revelation on April 8th, it was suggested that the theoretical single-core performance of the AMD Zen5 architecture could increase by over 40% compared to Zen4. The latest speculation from MLID indicates that the secret behind this boost likely lies in the AVX-512 instruction set.
Originally an exclusive feature of Intel, the AVX-512 instruction set found its way into the AMD Zen4 architecture, supporting both consumer-grade Ryzen and data center-grade EPYC processors. However, with Intel's next-generation Arrow Lake and Lunar Lake processors, which are likely to abandon AVX-512 support due to their use of a big.LITTLE core architecture design (and the absence of hyper-threading), it appears that AMD will now have the upper hand in this aspect.
The AVX-512 instruction set in the Zen4 architecture is executed through the combination of two 256-bit FPU floating-point units, offering a bit more flexibility and lower power consumption, albeit without reaching peak performance.
With the Zen5 architecture, a 512-bit FPU unit will be introduced, enabling direct execution of AVX-512 instructions. This enhancement not only boosts performance but also facilitates efficient execution of instructions like VNNI, thereby significantly enhancing AI capabilities.
To complement this upgrade, Zen5 architecture will see enhancements in other aspects as well. This includes expanding the size of the first-level cache DTLB, increasing the first-level data cache capacity from 32KB to 48KB, widening the load-store queue, reducing the latency of FPU MADD by one clock cycle, and more.
Additionally, the integer execution pipeline in the Zen5 architecture will be expanded from 8 stages to 10 stages.
However, the second-level cache capacity remains unchanged at 1MB per core.
